ISSCC 2007 / SESSION 22 / DIGITAL CIRCUIT INNOVATIONS / 22 . 5 22 . 5 A 1 . 6 pJ / bit 96 % Stable Chip - ID Generating Circuit using Process Variations

Many integrated circuit applications require a unique identification number (ID) on each die that can be read anytime during the lifetime of the chip. A robust read-only ID is important for labeling RFID tags, addressing low-power wireless sensor nodes, IC process quality control, and secure documentation. Traditional methods of writing addresses into ROMs involve external programming, incurring additional expense or process modifications. Recently, Lofstrom et al. proposed the extraction of a unique and repeatable ID from random variable mismatch [1], which led to new testing methodology capability, including inexpensive identification of packaged dice [2]. Published results in this area suggest that it is possible to extract a unique fingerprint from each chip by comparing the transistor current flow or digital path delay variations that exist from die to die [1,3]. In this work, we propose a new chip-ID generation circuit that relies on digitallatch threshold-offset voltages to provide a robust 128b ID. Using the large gain provided by cross-coupled logic gates, we achieve significant improvements in readout speed and power consumption over existing designs, allowing a minimum power consumption of 162nW at low clock rates and an energy per bit of 1.6pJ/bit at 1Mb/s.